1. Field of the Invention
The present invention relates to a frequency detector. More particularly, the present invention relates to a frequency detector detecting a variation in frequency difference between a data signal and a clock signal.
2. Description of the Background Art
A conventional frequency detector samples a clock signal by using both rise and fall of a data signal. An example thereof is a frequency detector described in “WA 20.5, A 1 Gb/s CMOS Clock and Data Recovery Circuit” (referred to as “WA 20.5” hereinafter) by Hui Wang et al., IEEE International Solid-State Circuits Conference, 1999 (ISSCC 1999).
The conventional frequency detector could make an erroneous determination as to how a frequency of a data signal increases or decreases with respect to a frequency of a clock signal, when a duty ratio of the data signal is corrupted or when the data signal successively has the same value. Here, “a duty ratio of a data signal is corrupted” means that a ratio (a duty ratio) of a remainder obtained from a division of a time of an H level data signal by a data cycle to a remainder obtained from a division of a time of an L level data signal by a data cycle is not 1 to 1.